List of top Nano Technology Questions

MOSFET cutoff occurs when:

Digital signals for FFT are assumed:

CMOS inverter output is LOW when input is:

A counter with modulus 8 has:

"Latch-up" in CMOS circuits is caused by the formation of parasitic:

In a MOSFET, if the source-to-body voltage \( V_{SB} > 0 \) (for NMOS), the threshold voltage \( V_T \):

D/A converter resolution improves with:

A 10-bit ADC has a reference voltage of 10.24 V. The resolution (step size) of the converter is:

A practical op-amp differentiator requires a small resistor in series with the input capacitor to:

A 4-bit ripple counter uses flip-flops with a propagation delay of 50 ns each. The maximum clock frequency that can be used is:

The characteristic of an ideal operational amplifier is

The process of converting a continuous-time signal into a discrete-time signal is called

Charge Coupled Devices (CCDs) are primarily used in

Which of the following logic gate is known as a "Universal Gate"?

A CMOS inverter consists of

How many flip-flops are required to design a Mod-10 counter?

CMOS technology is preferred for

BJT in common-emitter configuration has

Whenever a JFET operates above pinch-off voltage

DFT converts

Basic function of ADC is to convert

A half-adder has

Concrete is a classic example of which type of composite?

Quantum confinement effects become significant when the size of the particle is comparable to the

Integrator using op-amp uses