Question

CMOS inverter output is LOW when input is:

• A. LOW
• B. HIGH
• C. Floating
• D. Zero current

Hint:

In CMOS logic: NMOS transistors turn on with a HIGH input voltage and pass a strong LOW signal. PMOS transistors turn on with a LOW input voltage and pass a strong HIGH signal.

Answer 1

The Correct Option is B

Concept: A standard CMOS inverter consists of a complementary pair of transistors connected in series between the supply voltage \( V_{DD} \) and ground \( V_{SS} \):
• A Pull-Up Network featuring a PMOS transistor connected to \( V_{DD} \).
• A Pull-Down Network featuring an NMOS transistor connected to ground \( V_{SS} \). Both transistors share a common gate connection, which serves as the input terminal (\( V_{\text{in}} \)), and their drains are tied together to form the output terminal (\( V_{\text{out}} \)).

Step 1: Analyze transistor behavior when the input is HIGH (\( V_{\text{in}} = V_{DD} \)).
When a logical HIGH voltage level is applied to the input terminal:
• For the NMOS transistor, the gate-to-source voltage is \( V_{GS,n} = V_{DD} > V_{th,n} \). This turns the NMOS transistor ON, creating a low-resistance path between the output terminal and ground.
• For the PMOS transistor, the gate-to-source voltage is \( V_{GS,p} = V_{DD} - V_{DD} = 0 \). Since this value is above the negative threshold voltage \( V_{th,p} \), the PMOS transistor turns OFF, disconnecting the output terminal from \( V_{DD} \).

Step 2: Determine the output state.
Because the PMOS transistor is an open circuit and the NMOS transistor acts as a closed switch to ground, the output terminal is pulled directly down to the ground potential (\( V_{SS} \)). \[ V_{\text{out}} = 0\text{ V} \quad \Rightarrow \quad \text{Logical LOW} \]

Step 3: Verify the logic inversion operation.

• When \( V_{\text{in}} = \text{LOW} \), PMOS is ON and NMOS is OFF, pulling the output up to \( V_{DD} \) (\( \text{HIGH} \)).
• When \( V_{\text{in}} = \text{HIGH} \), NMOS is ON and PMOS is OFF, pulling the output down to ground (\( \text{LOW} \)). Therefore, the CMOS inverter output is LOW specifically when the input is HIGH.