Question

"Latch-up" in CMOS circuits is caused by the formation of parasitic:

• A. Capacitors
• B. Inductors
• C. Thyristors (SCRs)
• D. Resistors

Hint:

To prevent latch-up in physical integrated circuit designs, engineers implement guard rings (highly doped substrate taps) to collect stray carriers and minimize substrate resistance, keeping the parasitic thyristor from turning on.

Answer 1

The Correct Option is C

Concept: Latch-up is a critical failure mode observed in bulk Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits. It introduces a low-impedance path between the power supply rail (\( V_{DD} \)) and the ground rail (\( V_{SS} \)), effectively short-circuiting the power distribution net. This phenomenon is driven by the inadvertent creation of closely coupled parasitic bipolar junction transistors (BJTs) that behave exactly like a Silicon Controlled Rectifier (SCR) or thyristor.

Step 1: Analyze the underlying physical structure of CMOS devices.
A basic CMOS inverter contains adjacent PMOS and NMOS transistors.
• The PMOS transistor is built inside an n-well substrate, consisting of p+ source/drain diffusions.
• The NMOS transistor is built directly inside a p-type substrate, consisting of n+ source/drain diffusions. This close physical proximity creates unwanted cross-coupled semiconductor layer patterns: a \( p \)-type source/drain, an \( n \)-well, a \( p \)-substrate, and an \( n \)-type source/drain. This arrangement inherently acts as a four-layer \( p-n-p-n \) structure.

Step 2: Examine the parasitic transistor interaction.
This \( p-n-p-n \) structure establishes two cross-coupled parasitic BJTs:
• A parasitic PNP transistor (formed by the p+ source of PMOS, the n-well, and the p-substrate).
• A parasitic NPN transistor (formed by the n-well, the p-substrate, and the n+ source of NMOS). The collector of the PNP transistor feeds directly into the base of the NPN transistor, and the collector of the NPN transistor feeds back into the base of the PNP transistor. This circuit configuration forms a classic regenerative feedback loop—the precise equivalent circuit model of a thyristor (SCR).

Step 3: Understand the triggering condition.
When an unexpected noise spike, transient voltage overshoot, or radiation event injects current into the substrate or well, it creates a voltage drop across the inherent well/substrate resistances. If this local voltage drop exceeds roughly \( 0.7\text{ V} \), it forward-biases one of the parasitic base-emitter junctions. Once triggered, the regenerative current loop sustains itself even after the original noise source disappears. This low-impedance latch state draws massive current from the power supply, causing severe thermal stress and potential permanent hardware destruction unless the power is completely cycled. Therefore, latch-up is caused by these parasitic thyristors.