Concept:
In a paged memory system, every memory access requires two physical memory accesses: one to fetch the Page Table Entry (PTE) to find the frame number, and a second to actually access the data in that frame. This doubles the memory access time, which is a major performance hit. The TLB is a specialized, high-speed hardware cache designed to solve this.
Step 1: The Problem of Two-Step Access.
Without a TLB:
\[ \text{Effective Access Time (EAT)} = \text{Time to access Page Table} + \text{Time to access Data} \]
If memory access is 100ns, EAT becomes 200ns.
Step 2: The TLB as a Hardware Solution.
The TLB is an associative memory (Cache) located within the CPU's Memory Management Unit (MMU). It stores a small number of recently used mappings from the Page Table (Page Number $\to$ Frame Number).
• TLB Hit: The mapping is found in the TLB (takes $\approx$ 1ns). The physical address is generated instantly.
• TLB Miss: The mapping is not in the TLB. The CPU must then perform the slow search in the Page Table in main memory.
Step 3: Effective Access Time with TLB.
With a high hit ratio (e.g., 99%), the EAT is calculated as:
\[ \text{EAT} = (\text{Hit Ratio} \times \text{TLB Access Time}) + (\text{Miss Ratio} \times \text{Total Access Time}) \]
This brings the average speed very close to the speed of a single physical memory access, significantly boosting performance.