Question:
The values of \(Y\) and \(Z\) in the given logic circuit are
The values of \(Y\) and \(Z\) in the given logic circuit are
Show Hint
In logic circuits, solve gate by gate from left to right. Remember:
\[
\text{AND gives }1\text{ only when all inputs are }1
\]
\[
\text{OR gives }1\text{ if at least one input is }1
\]
NAND is the complement of AND
Updated On: Jun 24, 2026
- \(Y=1,\quad Z=1\)
- \(Y=0,\quad Z=1\)
- \(Y=1,\quad Z=0\)
- \(Y=0,\quad Z=0\)
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The Correct Option is A
Solution and Explanation
Step 1: Find the output of the upper AND gate.
The inputs to the upper AND gate are \[ 1 \quad \text{and} \quad 0 \] So, \[ 1\cdot 0=0 \]
Step 2: Find the output of the lower OR gate.
The inputs to the lower OR gate are \[ 0 \quad \text{and} \quad 1 \] So, \[ 0+1=1 \]
Step 3: Find the output of the middle OR gate.
The inputs to the middle OR gate are \(0\) and \(1\).
Therefore, \[ 0+1=1 \]
Step 4: Find the value of \(Y\).
The final upper gate is a NAND gate.
Its inputs are \[ 0 \quad \text{and} \quad 1 \] The AND output is \[ 0\cdot 1=0 \] Since it is a NAND gate, the output is the complement of \(0\).
Thus, \[ Y=\overline{0}=1 \]
Step 5: Find the value of \(Z\).
The lower OR gate output is \(1\), and after passing through NOT gate, it becomes \[ \overline{1}=0 \] Now the final OR gate has inputs \[ Y=1 \] and \[ 0 \] Therefore, \[ Z=1+0=1 \]
Step 6: Final conclusion.
Hence, \[ \boxed{Y=1,\quad Z=1} \]
The inputs to the upper AND gate are \[ 1 \quad \text{and} \quad 0 \] So, \[ 1\cdot 0=0 \]
Step 2: Find the output of the lower OR gate.
The inputs to the lower OR gate are \[ 0 \quad \text{and} \quad 1 \] So, \[ 0+1=1 \]
Step 3: Find the output of the middle OR gate.
The inputs to the middle OR gate are \(0\) and \(1\).
Therefore, \[ 0+1=1 \]
Step 4: Find the value of \(Y\).
The final upper gate is a NAND gate.
Its inputs are \[ 0 \quad \text{and} \quad 1 \] The AND output is \[ 0\cdot 1=0 \] Since it is a NAND gate, the output is the complement of \(0\).
Thus, \[ Y=\overline{0}=1 \]
Step 5: Find the value of \(Z\).
The lower OR gate output is \(1\), and after passing through NOT gate, it becomes \[ \overline{1}=0 \] Now the final OR gate has inputs \[ Y=1 \] and \[ 0 \] Therefore, \[ Z=1+0=1 \]
Step 6: Final conclusion.
Hence, \[ \boxed{Y=1,\quad Z=1} \]
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