Question

The initial contents of the 4-bit Serial in parallel out, right shift, shift register shown in figure is 0101. After three clock pulses, the contents of the shift register will be

• A. 1110
• B. 1100
• C. 0110
• D. 1010

Hint:

Create a simple transition table to avoid track-keeping errors:
Initial: 0 1 0 1 $\rightarrow$ XOR of last two bits (0 $\oplus$ 1 = 1) $\rightarrow$ Shift: 1 0 1 0.
Pulse 1: 1 0 1 0 $\rightarrow$ XOR of last two (1 $\oplus$ 0 = 1) $\rightarrow$ Shift: 1 1 0 1.
Pulse 2: 1 1 0 1 $\rightarrow$ XOR of last two (0 $\oplus$ 1 = 1) $\rightarrow$ Shift: 1 1 1 0.
This systematic tracking prevents calculation mistakes.

Answer 1

The Correct Option is A

Step 1: Understanding the Question:
The question asks to find the final state of a 4-bit right-shift register after 3 clock pulses. The register has an XOR gate in its feedback path, making it a Linear Feedback Shift Register (LFSR).

Step 2: Key Formula or Approach:
Let the 4 bits of the shift register from left to right be represented as \( Q_3, Q_2, Q_1, Q_0 \).
From the given schematic, we observe the connections:
- The feedback input to the left-most bit (\( Q_3 \)) is the output of the XOR gate.
- The inputs to the XOR gate are taken from the outputs of \( Q_1 \) and \( Q_0 \).
- Therefore, the feedback equation is:
\[ D_3 = Q_1 \oplus Q_0 \] - For a right shift register, the state transitions at each clock pulse are:
\[ Q_3(t+1) = Q_1(t) \oplus Q_0(t) \] \[ Q_2(t+1) = Q_3(t) \] \[ Q_1(t+1) = Q_2(t) \] \[ Q_0(t+1) = Q_1(t) \]

Step 3: Detailed Explanation:

• Identify the initial state of the shift register at \( t = 0 \):
\[ Q_3 Q_2 Q_1 Q_0 = 0101 \]
• First Clock Pulse:
Determine the feedback input:
\[ D_3 = Q_1 \oplus Q_0 = 0 \oplus 1 = 1 \] Shift the existing bits to the right and load \( D_3 \) into \( Q_3 \):
\[ Q_3 \leftarrow 1 \] \[ Q_2 \leftarrow 0 \] \[ Q_1 \leftarrow 1 \] \[ Q_0 \leftarrow 0 \] State after 1st clock pulse: \( 1010 \).

• Second Clock Pulse:
Determine the feedback input:
\[ D_3 = Q_1 \oplus Q_0 = 1 \oplus 0 = 1 \] Shift the existing bits to the right and load \( D_3 \) into \( Q_3 \):
\[ Q_3 \leftarrow 1 \] \[ Q_2 \leftarrow 1 \] \[ Q_1 \leftarrow 0 \] \[ Q_0 \leftarrow 1 \] State after 2nd clock pulse: \( 1101 \).

• Third Clock Pulse:
Determine the feedback input:
\[ D_3 = Q_1 \oplus Q_0 = 0 \oplus 1 = 1 \] Shift the existing bits to the right and load \( D_3 \) into \( Q_3 \):
\[ Q_3 \leftarrow 1 \] \[ Q_2 \leftarrow 1 \] \[ Q_1 \leftarrow 1 \] \[ Q_0 \leftarrow 0 \] State after 3rd clock pulse: \( 1110 \).