Question:
The given circuit consists of five logic gates. If the inputs are \(A=0\), \(B=1\), \(C=1\) and \(D=0\), then the outputs \((y_1,y_2)\) are respectively
The given circuit consists of five logic gates. If the inputs are \(A=0\), \(B=1\), \(C=1\) and \(D=0\), then the outputs \((y_1,y_2)\) are respectively
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Remember:
\[
\text{NAND}=(AB)',
\]
\[
\text{NOR}=(A+B)',
\]
\[
\text{OR}=A+B.
\]
Evaluate the outputs gate-by-gate from left to right.
Updated On: Jul 9, 2026
- \(1,1\)
- \(1,0\)
- \(0,1\)
- \(0,0\) \bigskip
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The Correct Option is A
Solution and Explanation
Concept:
The gates used are:
• Top gate: NAND
• Middle gate: NOR
• Bottom gate: OR
• Upper-right gate: OR
• Lower-right gate: NAND
Step 1: Evaluate the output of the top NAND gate. Inputs: \[ A=0,\qquad B=1. \] AND output: \[ A\cdot B=0. \] Hence NAND output is \[ X=(A\cdot B)'=(0)'=1. \]
Step 2: Evaluate the output of the middle NOR gate. Inputs: \[ B=1,\qquad C=1. \] OR output: \[ B+C=1. \] Therefore, \[ Y=(B+C)'=(1)'=0. \]
Step 3: Evaluate the output of the bottom OR gate. Inputs: \[ C=1,\qquad D=0. \] Hence, \[ Z=C+D=1+0=1. \]
Step 4: Find \(y_1\). The upper-right gate is an OR gate with inputs \(X\) and \(Y\). \[ y_1=X+Y. \] \[ y_1=1+0=1. \]
Step 5: Find \(y_2\). The lower-right gate is a NAND gate with inputs \(Y\) and \(Z\). \[ y_2=(YZ)'. \] \[ y_2=(0\times1)'. \] \[ y_2=(0)'. \] \[ y_2=1. \]
Step 6: Write the final answer. \[ \boxed{(y_1,y_2)=(1,1)} \] \[ \boxed{\text{Answer = (A)}} \]
• Top gate: NAND
• Middle gate: NOR
• Bottom gate: OR
• Upper-right gate: OR
• Lower-right gate: NAND
Step 1: Evaluate the output of the top NAND gate. Inputs: \[ A=0,\qquad B=1. \] AND output: \[ A\cdot B=0. \] Hence NAND output is \[ X=(A\cdot B)'=(0)'=1. \]
Step 2: Evaluate the output of the middle NOR gate. Inputs: \[ B=1,\qquad C=1. \] OR output: \[ B+C=1. \] Therefore, \[ Y=(B+C)'=(1)'=0. \]
Step 3: Evaluate the output of the bottom OR gate. Inputs: \[ C=1,\qquad D=0. \] Hence, \[ Z=C+D=1+0=1. \]
Step 4: Find \(y_1\). The upper-right gate is an OR gate with inputs \(X\) and \(Y\). \[ y_1=X+Y. \] \[ y_1=1+0=1. \]
Step 5: Find \(y_2\). The lower-right gate is a NAND gate with inputs \(Y\) and \(Z\). \[ y_2=(YZ)'. \] \[ y_2=(0\times1)'. \] \[ y_2=(0)'. \] \[ y_2=1. \]
Step 6: Write the final answer. \[ \boxed{(y_1,y_2)=(1,1)} \] \[ \boxed{\text{Answer = (A)}} \]
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