Question

Minimum number of 2-input NAND gates required for implementing the logic \( F = AB + A'C \) is:

• A. 3
• B. 4
• C. 5
• D. 6

Hint:

A 2-to-1 Multiplexer equation \( Y = I_1 S + I_0 S' \) always requires exactly 4 NAND gates.
Recognizing standard multiplexer logic expressions during exams saves calculation time.

Answer 1

The Correct Option is B

Step 1: Understanding the Question:
The question asks for the minimum number of 2-input NAND gates required to implement the Boolean function \( F = AB + A'C \).
This Boolean function is the characteristic equation of a 2-to-1 Multiplexer, where \( A \) acts as the select line, and \( B \) and \( C \) are the data inputs.

Step 2: Key Formula or Approach:
NAND gates are universal gates, which means any Boolean expression can be realized using only NAND gates.
To implement the function \( F = AB + A'C \), we can apply De Morgan's Law twice to convert the Sum-Of-Products (SOP) expression into a NAND-NAND structure:
\[ F = \overline{\overline{AB + A'C}} \] Using De Morgan's Law:
\[ F = \overline{(\overline{AB}) \cdot (\overline{A'C})} \]

Step 3: Detailed Explanation:
Let us systematically break down the construction of the logic using 2-input NAND gates:

• Gate 1 (Inverter): We first need to obtain the complement of \( A \), which is \( A' \). This is done by connecting the inputs of a 2-input NAND gate together:
\[ G_1 = \overline{A \cdot A} = A' \]
• Gate 2 (NAND term 1): Next, we perform a NAND operation on the inputs \( A \) and \( B \):
\[ G_2 = \overline{AB} \]
• Gate 3 (NAND term 2): We perform a NAND operation on the inverted input \( A' \) (from Gate 1) and the input \( C \):
\[ G_3 = \overline{A' \cdot C} \]
• Gate 4 (Final output): Finally, the outputs of Gate 2 and Gate 3 are connected to the inputs of a fourth NAND gate to complete the SOP realization:
\[ G_4 = \overline{G_2 \cdot G_3} = \overline{(\overline{AB}) \cdot (\overline{A'C})} = AB + A'C \] By tallying the gates used, we find that we have utilized exactly 4 gates in total.
Therefore, the minimum number of 2-input NAND gates required is 4.

Step 4: Final Answer:
The minimum number of 2-input NAND gates required to implement \( F = AB + A'C \) is 4.