In the following digital circuit, the delay of both the NAND gates is 4 nanoseconds (ns) and the delay of the NOT gate is 1 ns. If a 10 MHz clock signal with 50% duty cycle is given as the input, the duty cycle of the output is %. (Answer in integer)
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The circuit is a cross coupled NAND pair driven by Input and its delayed inverse, so it settles to Output = NOT(Input), but the rising and falling edges of Output take different total delays (4 ns vs 9 ns) because a NAND gate with one input forced to 0 does not need to wait on its other input.
Step 1: Understand the circuit.
The Input signal drives the top NAND gate directly on one input, and also drives a NOT gate (delay 1 ns) whose output goes to one input of the bottom NAND gate.
The top NAND gate's output is the Output of the circuit, and this Output is fed back as the second input of the bottom NAND gate.
The bottom NAND gate's output is fed back as the second input of the top NAND gate.
So this is a cross coupled NAND latch, where the two drive signals are the Input and its delayed inverse, not two independent control lines.
Step 2: Find the steady output level for each Input level.
Call the top NAND gate output \(Q_1\) (this is the circuit Output) and the bottom NAND gate output \(Q_2\).
\[ Q_1 = \overline{\text{Input} \cdot Q_2}, \qquad Q_2 = \overline{\overline{\text{Input}} \cdot Q_1} \]
When Input \(=1\): try \(Q_2=0\), then \(Q_1=\overline{1 \cdot 0}=1\); feed \(Q_1=1\) back, \(Q_2=\overline{0\cdot 1}=1\) (a NAND gate with a 0 input is always 1); recompute \(Q_1=\overline{1\cdot 1}=0\). This is stable, so for Input \(=1\), Output \(Q_1=0\).
When Input \(=0\): by the same steps, Output \(Q_1=1\).
So once everything settles, the circuit behaves like a plain inverter, Output \(=\overline{\text{Input}}\). The real question is how long each edge takes to settle, because the two paths carry different total delay.
Step 3: Time the Output's falling edge (triggered by an Input rising edge).
Before Input rises, Input \(=0\) so Output \(Q_1=1\), \(Q_2=0\).
At the rising edge, Input becomes \(1\) at once, but this alone cannot flip \(Q_1\), because \(Q_1=\overline{1\cdot Q_2}\) still depends on \(Q_2\), which has not changed yet.
The NOT gate output (feeding \(Q_2\)) needs \(1\) ns to fall from \(1\) to \(0\). Once that happens, \(Q_2\) sees a changed input and needs its own \(4\) ns to switch from \(0\) to \(1\). Only then does \(Q_1\) see a changed \(Q_2\) and needs a further \(4\) ns to fall from \(1\) to \(0\).
Total delay for this Output falling edge \(= 1 + 4 + 4 = 9\) ns after the Input rising edge.
Step 4: Time the Output's rising edge (triggered by an Input falling edge).
Before Input falls, Input \(=1\) so Output \(Q_1=0\), \(Q_2=1\).
At the falling edge, Input becomes \(0\) at once. Now \(Q_1=\overline{0\cdot Q_2}\), and a NAND gate with one input already at \(0\) is forced to \(1\) no matter what \(Q_2\) is, so the top gate does not need to wait on \(Q_2\) at all.
So \(Q_1\) rises after just its own gate delay of \(4\) ns.
Total delay for this Output rising edge \(= 4\) ns after the Input falling edge.
Step 5: Build the timing for one full clock period.
The clock frequency is \(10\) MHz, so the period is
\[ T = \frac{1}{10 \times 10^6} = 100 \text{ ns} \]
With 50% duty cycle, Input is high for \(50\) ns and low for \(50\) ns. Take Input rising edges at \(t=0\) ns and \(t=100\) ns, and the Input falling edge at \(t=50\) ns.
Using Step 3 and Step 4: Output falls at \(t = 0+9 = 9\) ns; Output rises at \(t = 50+4 = 54\) ns; Output falls again at \(t = 100+9 = 109\) ns.
So Output is low from \(9\) ns to \(54\) ns, a duration of \(54-9=45\) ns, and Output is high from \(54\) ns to \(109\) ns, a duration of \(109-54=55\) ns.
Since \(45+55=100\) ns matches the period, this timing is self consistent.
