In the circuit diagram shown below, the logic gates operate with a supply voltage of 1 V. NAND and XNOR have 200 ps and 400 ps input-to-output delay, respectively. At time \( t = T \), \( A(t) = 0 \), \( B(t) = 1 \) and \( Z(t) = 0 \). When the inputs are changed to \( A(t) = 1 \), \( B(t) = 0 \) at \( t = 2T \), a 1 V pulse is observed at \( Z \). The pulse width of the 1 V pulse is _________ ps.
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In digital circuits, the pulse width depends on the sum of the propagation delays through the gates. Always account for the delays of each gate in the signal path.
Step 1: Understand the delay behavior of the gates.
The NAND gate has a delay of 200 ps and the XNOR gate has a delay of 400 ps. The total delay in the pulse width is the sum of the delays of the gates that the signal passes through.
Step 2: Analyze the changes in inputs and the resulting pulse.
Initially, when \( A(t) = 0 \) and \( B(t) = 1 \), the output \( Z(t) \) is low. When \( A(t) \) is changed to 1 and \( B(t) \) is changed to 0, the output \( Z \) switches to high after the delays of the NAND and XNOR gates. The total delay from the changes in the inputs is the sum of the NAND gate's delay (200 ps) and the XNOR gate's delay (400 ps), totaling 600 ps.
Step 3: Conclusion.
Since a pulse is observed at \( Z \), and considering the propagation delays, the pulse width is determined by the delays in the circuit, which are 200 ps in total for the transition of the 1 V signal.
Thus, the correct answer is (B) 200.
