Consider a system with 1 MB physical memory and a word length of 1 byte. The
system uses a direct mapped cache, with block numbers starting from 0. The word
with physical address 0xA2C28 is mapped to the cache block number 17610. The
maximum possible size of the cache (in KB) for this configuration is ___________.
(answer in integer)
Note: 1K=210 and 1M=220
Step 1: Convert the given physical address to binary form. The address is \(0xA2C28\), and physical memory is 1 MB = \(2^{20}\) bytes, so the physical address has 20 bits.
Step 2: In a direct mapped cache, the cache block number is obtained from the line-index bits of the physical address after removing the block-offset bits. The given cache block number is \(176_{10}\). Since \(176 = 128 + 32 + 16 = (10110000)_2\), the visible line-index suffix must be \(10110000\).
Step 3: The address \(0xA2C28\) in binary is \(1010\,0010\,1100\,0010\,1000\). To get decimal 176 as the cache block number, take a block offset of 6 bits. Then the index field begins after the lower 6 bits, and the next 11 index bits end with \(00010110000_2 = 176\).
Step 4: Therefore, the largest possible cache uses 6 offset bits and 11 index bits. The cache size is \[2^6 imes 2^{11} = 2^{17} ext{ bytes} = 128 ext{ KB}.\]
\[\boxed{128\text{ KB}}\]
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?

Match each addressing mode in List I with a data element or an element of a data
structure (in a high-level language) in List II:
List I
List II
P. Immediate
1. Element of an array
Q. Indirect
2. Pointer
R. Base with index
3. Element of a record
S. Base with offset/displacement 4. Constant
Consider the 8-bit signed integers 𝑋, 𝑌 and 𝑍 represented using the sign-magnitude
form. The binary representations of 𝑋 and 𝑌 are as follows:
𝑋: 10110100 𝑌: 01001100
Which of the following operations to compute 𝑍 result(s) in an arithmetic
overflow?
In a system, numbers are represented using 4-bit two’s complement form. Consider
four numbers 𝑁1 =1011, 𝑁2 =1101, 𝑁3 =1010 and 𝑁4 =1001 in the system.
Which of the following operations will result in arithmetic overflow?
The 32-bit IEEE 754 single precision representation of a number is 0xC2710000.
The number in decimal representation is ________. (rounded off to two decimal
places)
Consider the following two statements about interrupt handling mechanisms in a
CPU.
S1: In non-vectored interrupt mechanism, it usually takes more time to start the
Interrupt Service Routine (ISR) when compared to that in a vectored interrupt
mechanism.
S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices
individually to determine the source of the interrupt.
Which one of the following options is correct with respect to S1 and S2 ?