A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?

Identify the ONE CORRECT matching between the OSI layers and their corresponding functionalities as shown.

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

The height of any rooted tree is defined as the maximum number of edges in the path from the root node to any leaf node. Suppose a Min-Heap \( T \) stores 32 keys. The height of \( T \) is ___________ (Answer in integer).
Which one of the following dependencies among the register operands of different
instructions can cause a data hazard in a pipelined processor?
The EX stage of a pipelined processor performs the memory read operations for
LOAD instructions, and the operations for the arithmetic and logic instructions. Let
𝑡𝐸𝑋 denote the time taken by the EX stage to perform the operation for an instruction.
For each instruction type, the values of 𝑡𝐸𝑋 and M (the number of instructions of that
type in a sequence of 100 instructions for a program P), are given in the table below.
The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time
for the interstage buffers in the pipeline is negligible.
When program P is executed, the number of clock cycles for which the pipeline is
stalled due to structural hazards in the EX stage is ______. (answer in integer)
Instruction
𝑡𝐸𝑋 in
nanoseconds
𝑀
LOAD
1.8
15
IMUL
1.5
10
IDIV
2.5
5
FADD
1.7
10
FSUB
1.7
5
FMUL
2.8
15
FDIV
3.2
5
All other
instructions
Less than
1.0
35