In a system, numbers are represented using 4-bit twoβs complement form. Consider
four numbers π1 =1011, π2 =1101, π3 =1010 and π4 =1001 in the system.
Which of the following operations will result in arithmetic overflow?
We are working with 4-bit two's complement numbers. First, decode each given binary number to its signed decimal value.
Step 1: Decode the numbers. \(N_1 = 1011\): value \(= -8+0+2+1 = -5\). \(N_2 = 1101\): value \(= -8+4+0+1 = -3\). \(N_3 = 1010\): value \(= -8+0+2+0 = -6\). \(N_4 = 1001\): value \(= -8+0+0+1 = -7\).
Step 2: Recall the overflow rule. In an \(n\)-bit two's complement adder, overflow occurs exactly when the carry into the sign bit differs from the carry out of the sign bit.
Step 3: Check \(N_1 + N_2\). \(-5 + (-3) = -8\), which lies inside \([-8,7]\). Adding \(1011 + 1101\): carry into sign bit \(=1\), carry out of sign bit \(=1\), so no overflow. Result bits \(1000 = -8\), which is correct.
Step 4: Check \(N_2 + N_3\). \(-3 + (-6) = -9\), outside \([-8,7]\) - overflow expected. Adding \(1101+1010\): carry into sign bit \(=0\), carry out of sign bit \(=1\) - these differ, so overflow occurs.
Step 5: Check \(N_3 - N_4\). \(-6 - (-7) = 1\), inside \([-8,7]\). Subtraction becomes \(N_3 + (\text{two's complement of } N_4)\); two's complement of \(1001\) is \(0111 = 7\). Adding \(1010+0111\): carry into sign bit \(=1\), carry out of sign bit \(=1\) - equal, so no overflow. Result bits \(0001 = 1\), correct.
Step 6: Check \(N_1 + N_4\). \(-5 + (-7) = -12\), outside \([-8,7]\) - overflow expected. Adding \(1011+1001\): carry into sign bit \(=0\), carry out of sign bit \(=1\) - these differ, so overflow occurs.
Final Answer: Overflow occurs in \(N_2+N_3\) and \(N_1+N_4\). \(\boxed{\text{Options B and D}}\)
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?

Match each addressing mode in List I with a data element or an element of a data
structure (in a high-level language) in List II:
List I
List II
P. Immediate
1. Element of an array
Q. Indirect
2. Pointer
R. Base with index
3. Element of a record
S. Base with offset/displacement 4. Constant
Consider the 8-bit signed integers π, π and π represented using the sign-magnitude
form. The binary representations of π and π are as follows:
π: 10110100 π: 01001100
Which of the following operations to compute π result(s) in an arithmetic
overflow?
The 32-bit IEEE 754 single precision representation of a number is 0xC2710000.
The number in decimal representation is ________. (rounded off to two decimal
places)
Consider the following two statements about interrupt handling mechanisms in a
CPU.
S1: In non-vectored interrupt mechanism, it usually takes more time to start the
Interrupt Service Routine (ISR) when compared to that in a vectored interrupt
mechanism.
S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices
individually to determine the source of the interrupt.
Which one of the following options is correct with respect to S1 and S2 ?
Consider the real valued variables X, Y and Z represented using the IEEE 754 single-
precision floating-point format. The binary representations of X and Y in hexadecimal
notation are as follows:
X: 35C00000 Y: 34A00000
Let π = π+ π.
Which one of the following is the binary representation of π, in hexadecimal
notation?