Match each addressing mode in List I with a data element or an element of a data
structure (in a high-level language) in List II:
List I
List II
P. Immediate
1. Element of an array
Q. Indirect
2. Pointer
R. Base with index
3. Element of a record
S. Base with offset/displacement 4. Constant
We must match each addressing mode with the kind of high-level-language data element it is typically used to access.
Step 1: P. Immediate addressing.
In immediate addressing, the operand value is embedded directly in the instruction itself - there is no memory access to fetch the operand. This directly corresponds to a constant in a high-level language (item 4). So P -> 4.
Step 2: Q. Indirect addressing.
In indirect addressing, the instruction holds the address of a location that itself contains the address of the operand (an address of an address). This is exactly how a pointer variable works in a high-level language - the pointer holds an address that must be dereferenced to reach the data. So Q -> 2.
Step 3: R. Base with index addressing.
Here the effective address is computed as base register + index register, and the index is typically varied (e.g., in a loop) to walk through consecutive memory locations. This is the standard way compilers implement access to an element of an array - base = array start address, index = the array subscript. So R -> 1.
Step 4: S. Base with offset/displacement addressing.
Here the effective address is base register + a fixed constant offset known at compile time. This is exactly how a compiler accesses a specific named field inside a structure - base = address of the record/structure, offset = the fixed byte distance to that particular field. So S -> 3, i.e., element of a record.
Step 5: Combine the matches.
P-4, Q-2, R-1, S-3.
Final Answer: P-4, Q-2, R-1, S-3, option (B).
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?

Consider the 8-bit signed integers 𝑋, 𝑌 and 𝑍 represented using the sign-magnitude
form. The binary representations of 𝑋 and 𝑌 are as follows:
𝑋: 10110100 𝑌: 01001100
Which of the following operations to compute 𝑍 result(s) in an arithmetic
overflow?
In a system, numbers are represented using 4-bit two’s complement form. Consider
four numbers 𝑁1 =1011, 𝑁2 =1101, 𝑁3 =1010 and 𝑁4 =1001 in the system.
Which of the following operations will result in arithmetic overflow?
The 32-bit IEEE 754 single precision representation of a number is 0xC2710000.
The number in decimal representation is ________. (rounded off to two decimal
places)
Consider the following two statements about interrupt handling mechanisms in a
CPU.
S1: In non-vectored interrupt mechanism, it usually takes more time to start the
Interrupt Service Routine (ISR) when compared to that in a vectored interrupt
mechanism.
S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices
individually to determine the source of the interrupt.
Which one of the following options is correct with respect to S1 and S2 ?
Consider the real valued variables X, Y and Z represented using the IEEE 754 single-
precision floating-point format. The binary representations of X and Y in hexadecimal
notation are as follows:
X: 35C00000 Y: 34A00000
Let 𝑍 = 𝑋+ 𝑌.
Which one of the following is the binary representation of 𝑍, in hexadecimal
notation?