Question

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an
average of 5 clock cycles to complete the execution of an instruction. To improve
the performance, the system was pipelined with a goal of achieving an average
throughput of one instruction per clock cycle. However, it could operate only at
1.2 GHz due to pipeline overheads. While executing a program in the pipelined
design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards.
The speed-up obtained by the pipelined design over the non-pipelined one for this
program is ___________. (rounded off to two decimal places)
Note: 1G=109

Hint:

Find time per instruction for each design (Time = CPI x Clock Period), where pipelined CPI = 1 + (fraction stalled x stall cycles) = 1 + 0.3x2 = 1.6. Then Speed-up = Time(non-pipelined) / Time(pipelined).

Answer 1

Correct Answer: 2.3

We need to find the actual speed-up achieved by the pipelined processor over the non-pipelined processor for the given program, accounting for pipeline stalls.

Step 1: Compute execution time per instruction for the non-pipelined design.

Clock frequency = 1.6 GHz, so clock period \(T_{np} = \dfrac{1}{1.6 \times 10^9} = 0.625\) ns.

Average CPI (non-pipelined) = 5 cycles per instruction.

Execution time per instruction (non-pipelined):

\[T_{np,\ inst} = 5 \times 0.625\ \text{ns} = 3.125\ \text{ns}\]

Step 2: Compute the effective CPI for the pipelined design.

Ideally the pipeline achieves 1 instruction per cycle (CPI = 1). However, 30% of instructions face a stall of 2 extra cycles due to hazards.

Effective CPI:

\[CPI_{eff} = 1 + (0.30 \times 2) = 1 + 0.6 = 1.6\]

Step 3: Compute execution time per instruction for the pipelined design.

Clock frequency = 1.2 GHz, so clock period \(T_p = \dfrac{1}{1.2 \times 10^9} = 0.8333\) ns.

Execution time per instruction (pipelined):

\[T_{p,\ inst} = CPI_{eff} \times T_p = 1.6 \times 0.8333\ \text{ns} = 1.3333\ \text{ns}\]

Step 4: Compute the speed-up.

Speed-up is the ratio of execution time of the non-pipelined design to the execution time of the pipelined design (for the same program, i.e., same number of instructions, so the instruction count cancels out):

\[\text{Speed-up} = \dfrac{T_{np,\ inst}}{T_{p,\ inst}} = \dfrac{3.125}{1.3333}\]\[\text{Speed-up} = 2.34375 \approx 2.34\]

Step 5: Conclusion.

The speed-up of the pipelined design over the non-pipelined design lies between 2.30 and 2.40, matching the official key.

Final Answer: \[\boxed{2.34\ (\text{accepted range: } 2.30\ \text{to}\ 2.40)}\]