Step 1: An FPGA is built from a grid of programmable blocks connected by routing. The block that actually realises user logic is the Configurable Logic Block (CLB).
Step 2: Each CLB contains look-up tables (LUTs) that implement any combinational function, plus flip-flops that store state for sequential logic. Together they cover both combinational and sequential designs.
Step 3: Look at the other parts. DSP blocks are dedicated to fast multiply and add operations, a Phase-Locked Loop handles clock generation and timing, and Block RAM stores data. None of these is the general logic fabric.
Step 4: So the component responsible for implementing combinational and sequential logic is the Configurable Logic Block, option (C).