Question

The circuit shown in figure is

• A. NAND
• B. NOR
• C. AND
• D. OR

Hint:

CMOS NAND has NMOS in series and PMOS in parallel. This arrangement gives output LOW only when both inputs are HIGH.

Answer 1

The Correct Option is A

The image shows a CMOS-based logic circuit consisting of two PMOS transistors in parallel and two NMOS transistors in series. This is a classic configuration of a NAND gate.

Truth Table of NAND gate:
\[ \begin{array}{c c | c} \text{A} & \text{B} & \text{Y (Output)} \\ \hline 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \\ \end{array} \]
The circuit works by providing a LOW output only when both NMOS are conducting (inputs high), which confirms NAND logic.

Final Answer: (1) NAND