Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the “hit rate” for L1 cache is 90% while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the “hit rate” is 80% and the “miss penalty” for transferring data from L2 cache to L1 cache is 10 ns. The “miss penalty” for the data to be transferred from main memory to L2 cache is 100 ns. Then the average memory access time in this system in nanoseconds is ___________ . (rounded off to one decimal place)
Show Hint
Solution and Explanation
The formula for average memory access time (AMAT) in a system with two cache levels is: \[ {AMAT} = {Hit time}_{L1} + {Miss rate}_{L1} \times ({Hit time}_{L2} + {Miss rate}_{L2} \times {Miss penalty}_{L2}) \] Step 1: Given Data - \( {Hit time}_{L1} = 1 \) ns - \( {Hit rate}_{L1} = 0.90 \Rightarrow {Miss rate}_{L1} = 1 - 0.90 = 0.10 \) - \( {Hit time}_{L2} = 10 \) ns - \( {Hit rate}_{L2} = 0.80 \Rightarrow {Miss rate}_{L2} = 1 - 0.80 = 0.20 \) - \( {Miss penalty}_{L2} = 100 \) ns
Step 2: Compute AMAT \[ {AMAT} = 1 + (0.10 \times (10 + (0.20 \times 100))) \] \[ = 1 + (0.10 \times (10 + 20)) \] \[ = 1 + (0.10 \times 30) = 1 + 3 = 4.0 { ns} \]
Top GATE CS Computer Science and IT Engineering Questions
- Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:
(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.
Which ONE of the following is the CORRECT sequence of steps? - Which ONE of the following statements is FALSE regarding the symbol table?
- Which ONE of the following techniques used in compiler code optimization uses live variable analysis?
- Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?
Top GATE CS Operating Systems Questions
- Which of the following is/are part of an Instruction Set Architecture of a processor?
- Suppose we are transmitting frames between two nodes using the Stop-and-Wait protocol. The frame size is 3000 bits. The transmission rate of the channel is 2000 bps (bits/second) and the propagation delay between the two nodes is 100 milliseconds. Assume that the processing times at the source and destination are negligible. Also, assume that the size of the acknowledgement packet is negligible. Which ONE of the following most accurately gives the channel utilization for the above scenario in percentage?
Consider a system with the following: - \(\mathbb{P} = \{ P_1, P_2, P_3, P_4 \}\) consists of all active processes in an operating system. - \(\mathbb{R} = \{ R_1, R_2, R_3, R_4 \}\) consists of single instances of distinct types of resources in the system.
The resource allocation graph has the following assignment and claim edges: Assignment edges: \[ R_1 \to P_1, \quad R_2 \to P_2, \quad R_3 \to P_3, \quad R_4 \to P_4 \] (The assignment edge \( R_1 \to P_1 \) means resource \( R_1 \) is assigned to process \( P_1 \), and so on for others.)
Claim edges: \[ P_1 \to R_2, \quad P_2 \to R_3, \quad P_3 \to R_1, \quad P_2 \to R_4, \quad P_4 \to R_2 \] (The claim edge \( P_1 \to R_2 \) means process \( P_1 \) is waiting for resource \( R_2 \), and so on for others.)
Which of the following statement(s) is/are CORRECT?- A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ___________ . (rounded off to two decimal places)
Top GATE CS Questions
- Which of the following sequences when stored in an array at locations A[1],..., A[10] forms a max-heap?
- The Lucas sequence Ln is defined by the recurrence relation: Ln = Ln−1 + Ln−2, for n ≥ 3, with L1 = 1 and L2 = 3. Which one of the options given is TRUE?
- Which of the following fields of IP header is/are always modified by any router before it forwards to IP Packet ?
- Which one of the following CIDR profix exactly represent the range of IP addresses 10.12.2.0 to 10.12.3.255?
- Consider an ethernet segment whose transmission is \(10^8\) bits per second. Maximum segment length \(500\ m\), speed of the provocation media velocity is \(2 × 10^8\) meter per second. What is the minimum frame size in bits ?