The time per instruction cycle in a pipelined system is given by: \[ {Cycle time} = \max({Stage delays}) + {Latch delay} \] Step 1: Given Data - Stage delays: \( 180, 250, 150, 170, 250 \) ns - Maximum stage delay: \( 250 \) ns - Inter-stage latch delay: \( 10 \) ns
Step 2: Compute Cycle Time \[ {Cycle time} = 250 + 10 = 260 { ns} \] Step 3: Compute Total Execution Time Since the pipeline fills in the first 5 cycles, the total execution time for \( n \) instructions is: \[ {Time} = ({Pipeline fill time} + (n - 1) \times {Cycle time}) \] \[ = (5 \times 260) + (999 \times 260) \] \[ = 1300 + 259740 = 261040 { ns} = 261.04 { µs} \] Thus, the answer is between \( 260.20 \) and \( 261.20 \) µs.