Question

For the circuit shown in the figure, the delay of the bubbled NAND gate is 5 ns and that of the counter is assumed to be zero. If the clock (Clk) frequency is 12 MHz, then the counter behaves as a ________.

• A. mod-5 counter
• B. mod-6 counter
• C. mod-7 counter
• D. mod-8 counter

Hint:

A 3-bit counter cycles through 8 states (0–7). If not reset early, it behaves as mod-8.

Answer 1

The Correct Option is D

Step 1: The given system is a 3-bit synchronous counter. A 3-bit counter counts from 000 to 111, i.e., 0 to 7.
Step 2: That gives 8 unique states, so by default it behaves as a mod-8 counter.
Step 3: Feedback from outputs and a NAND gate is sometimes used to reset the counter early and create mod-N counters (where \( N<2^n \)).
Step 4: However, the delay of 5 ns in the NAND gate is too small to cause premature reset at the current frequency (12 MHz clock = 83.33 ns period), so the counter completes all 8 states.
Thus, the counter behaves as a mod-8 counter.