Question:
A packet with the destination IP address 145.36.109.70 arrives at a router whose routing table is shown. Which interface will the packet be forwarded to?
A packet with the destination IP address 145.36.109.70 arrives at a router whose routing table is shown. Which interface will the packet be forwarded to?
Show Hint
When checking a destination IP address against a routing table, compare it with each subnet using the subnet mask and find the longest matching prefix.
Updated On: Jan 30, 2026
- E1
- E2
- E3
- E5
Show Solution
Verified By Collegedunia
The Correct Option is A
Solution and Explanation
We are given the destination IP address \( 145.36.109.70 \), and we need to find which interface the packet will be forwarded to based on the routing table.
1. Convert the IP address to binary form:
The given IP address is \( 145.36.109.70 \), and in binary form it is: \[ 145 = 10010001, \quad 36 = 00100100, \quad 109 = 01101101, \quad 70 = 01000110 \] So, the binary form of \( 145.36.109.70 \) is: \[ 10010001.00100100.01101101.01000110 \]
2. Check against the routing table:
For Subnet
The subnet address
The given IP address
3. Conclusion:
Since the IP address \( 145.36.109.70 \) falls under the subnet
Thus, the correct answer is \( \boxed{A} \).
1. Convert the IP address to binary form:
The given IP address is \( 145.36.109.70 \), and in binary form it is: \[ 145 = 10010001, \quad 36 = 00100100, \quad 109 = 01101101, \quad 70 = 01000110 \] So, the binary form of \( 145.36.109.70 \) is: \[ 10010001.00100100.01101101.01000110 \]
2. Check against the routing table:
For Subnet
145.36.0.0/16:
The subnet address
145.36.0.0 with the subnet mask /16 covers addresses from 145.36.0.0 to 145.36.255.255.
The given IP address
145.36.109.70 falls within this range. Therefore, it matches this subnet.
3. Conclusion:
Since the IP address \( 145.36.109.70 \) falls under the subnet
145.36.0.0/16, it will be forwarded to Interface E1.
Thus, the correct answer is \( \boxed{A} \).
Was this answer helpful?
0
0
Top GATE CS Computer Science and IT Engineering Questions
- Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:
(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.
Which ONE of the following is the CORRECT sequence of steps? - Which ONE of the following statements is FALSE regarding the symbol table?
- Which ONE of the following techniques used in compiler code optimization uses live variable analysis?
- Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?
View More Questions
Top GATE CS Computer Architecture Questions
- A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?
- Given Data:
- Two processors: \( M_1 \) and \( M_2 \)
- Four processes: \( P_1, P_2, P_3, P_4 \)
- CPU bursts: \( P_1 = 20 \), \( P_2 = 16 \), \( P_3 = 25 \), \( P_4 = 10 \)
- Priority order for \( M_1 \): \( P_1 > P_3 > P_2 > P_4 \)
- Priority order for \( M_2 \): \( P_2 > P_3 > P_4 > P_1 \)
- Scheduling: Non-preemptive priority scheduling
Step 1: Assigning Processes to Processors
At \( t = 0 \), both processors are free. The highest-priority process for each processor is scheduled:
- \( M_1 \) gets \( P_1 \) (highest priority on \( M_1 \), burst = 20 ms).
- \( M_2 \) gets \( P_2 \) (highest priority on \( M_2 \), burst = 16 ms).
Step 2: Scheduling Remaining Processes
- \( P_2 \) finishes at \( t = 16 \), so \( M_2 \) picks the next highest-priority process, \( P_3 \) (burst = 25 ms).
- \( P_1 \) finishes at \( t = 20 \), so \( M_1 \) picks \( P_4 \) (burst = 10 ms).
- \( P_4 \) finishes at \( t = 30 \), and \( P_3 \) finishes at \( t = 41 \).
Step 3: Calculate Waiting Times
- \( P_1 \) starts at 0, so waiting time = \( 0 \) ms.
- \( P_2 \) starts at 0, so waiting time = \( 0 \) ms.
- \( P_3 \) starts at 16, so waiting time = \( 16 \) ms.
- \( P_4 \) starts at 20, so waiting time = \( 20 \) ms.
Step 4: Compute Average Waiting Time
\[ \text{Average waiting time} = \frac{(0 + 0 + 16 + 20)}{4} = \frac{36}{4} = 9 \text{ ms}. \]
Final Answer: The average waiting time of the processes is \( 9 \) milliseconds. - An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with a 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET. Find the number of bits in the TAG.
- Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns for the first, second, and third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is ________ ns. Consider a processor P whose instruction set architecture is the load-store
architecture. The instruction format is such that the first operand of any instruction
is the destination operand.
Which one of the following sequences of instructions corresponds to the high-level
language statement Z = X + Y ?
Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.
Top GATE CS Questions
- Which of the following sequences when stored in an array at locations A[1],..., A[10] forms a max-heap?
- The Lucas sequence Ln is defined by the recurrence relation: Ln = Ln−1 + Ln−2, for n ≥ 3, with L1 = 1 and L2 = 3. Which one of the options given is TRUE?
- Which of the following fields of IP header is/are always modified by any router before it forwards to IP Packet ?
- Which one of the following CIDR profix exactly represent the range of IP addresses 10.12.2.0 to 10.12.3.255?
- Consider an ethernet segment whose transmission is \(10^8\) bits per second. Maximum segment length \(500\ m\), speed of the provocation media velocity is \(2 × 10^8\) meter per second. What is the minimum frame size in bits ?
View More Questions