Question

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

• A. Read-after-read
• B. Read-after-write
• C. Write-after-read
• D. Write-after-write

Hint:

A later instruction reading a register before an earlier instruction has written its new value into that register is the read-after-write (true dependency) hazard.

Answer 1

The Correct Option is B

Step 1: Recall the classification of register dependencies. When two instructions in a pipeline reference the same register, the dependency is classified by the order of the two accesses, Read-after-read (RAR), Read-after-write (RAW), Write-after-read (WAR), and Write-after-write (WAW).

Step 2: Read-after-read (RAR). Both instructions only read the register, neither changes its value, so the order in which they read it does not matter. This is not a real dependency and cannot cause any hazard.

Step 3: Read-after-write (RAW), a true data dependency. An earlier instruction writes a register and a later instruction needs that same register as a source operand. If the pipeline lets the later instruction read the register before the earlier instruction has actually written its new value, because their execution overlaps, the later instruction uses a stale value and computes the wrong result. This is a genuine data hazard, and it is why pipelined processors need forwarding or stalls.

Step 4: Write-after-read (WAR), an anti-dependency. An earlier instruction reads a register and a later instruction writes to it. This only becomes a hazard if instructions can complete out of program order, letting the later write happen before the earlier read occurs. In a simple in-order pipeline, operands are read strictly in program order, so the earlier instruction always reads the register before the later one can write it, no hazard occurs.

Step 5: Write-after-write (WAW), an output dependency. Two instructions both write the same register. This is only a hazard if the writes can be reordered so the earlier write happens after the later one, leaving the wrong final value. This again needs out-of-order completion, which a basic in-order pipeline does not have.

Step 6: Conclusion. Among the four options, only Read-after-write is a true dependency that causes a data hazard in an ordinary pipelined processor, since it reflects genuine data flow from producer to consumer, unlike WAR and WAW which are artifacts of register reuse that only matter under out-of-order execution, and unlike RAR which is not a dependency at all.

\[ \boxed{\text{Read-after-write}} \]