Question

Which one of the following dependencies among the register operands of different
instructions can cause a data hazard in a pipelined processor?

• A. Read-after-read
• B. Read-after-write
• C. Write-after-read
• D. Write-after-write

Hint:

Only a dependency where a later instruction reads a value before an earlier instruction has written it can give a wrong result in an in-order pipeline - that is the Read-after-Write (RAW) hazard.

Answer 1

The Correct Option is B

A pipelined processor overlaps the execution of successive instructions. A data hazard occurs when an instruction depends on the result of an earlier instruction that has not yet completed.

Step 1: List the possible register-dependency types between two instructions \(I_1\) (earlier) and \(I_2\) (later) that share a register:

• Read-after-Read (RAR): both instructions only read the register - no ordering constraint, not a hazard.
• Read-after-Write (RAW): \(I_2\) reads a register that \(I_1\) writes - true data dependency.
• Write-after-Read (WAR): \(I_2\) writes a register that \(I_1\) reads - anti-dependency.
• Write-after-Write (WAW): \(I_2\) writes a register that \(I_1\) also writes - output dependency.

Step 2: In a simple in-order pipeline, instructions are fetched, decoded, executed, and written back strictly in program order. Reads (operand-fetch stage) always precede a later instruction's write-back stage, so WAR and WAW situations cannot actually be violated, and RAR involves no real dependency.

Step 3: Only RAW creates a genuine hazard: \(I_2\) may try to read the register in its operand-fetch stage before \(I_1\) has written the correct value back, giving an incorrect (stale) value unless the pipeline stalls or forwards the result.

\[\boxed{\text{Answer: Read-after-write (Option B)}}\]