Question:
Which of the following is a universal gate ?
Which of the following is a universal gate ?
Show Hint
Just remember: "NAND and NOR can do it all." Basic gates (AND/OR/NOT) always need friends to complete a circuit.
Updated On: Jun 6, 2026
- AND
- OR
- NAND
- Inverter
Show Solution
Verified By Collegedunia
The Correct Option is C
Solution and Explanation
A "Universal Gate" is a logic gate that can be used to implement any other Boolean function (AND, OR, NOT, etc.) without needing any other type of gate.
1. Standard Universal Gates:
There are two primary universal gates in digital electronics:
• NAND (NOT AND)
• NOR (NOT OR) 2. Why Basic Gates are not Universal: Gates like AND, OR, and NOT (Inverter) are not universal on their own because you cannot build an OR gate using only AND gates, nor can you build an AND gate using only OR gates. You need a combination of them. 3. Conclusion: Since NAND is provided in the options, and it is capable of creating any digital circuit alone, it is the correct answer.
• NAND (NOT AND)
• NOR (NOT OR) 2. Why Basic Gates are not Universal: Gates like AND, OR, and NOT (Inverter) are not universal on their own because you cannot build an OR gate using only AND gates, nor can you build an AND gate using only OR gates. You need a combination of them. 3. Conclusion: Since NAND is provided in the options, and it is capable of creating any digital circuit alone, it is the correct answer.
Was this answer helpful?
0
0
Top CUET PG Data Science A.I Cyber Security and Computer Sci. Questions
- Choose the correct answer from the options given below:
(A). RAID 3 requires only a single redundant disk.
(B) In RAID 4 scheme, two different parity calculations are carried out and stored in separate blocks on different disks.
(C) RAID 5 distributes the parity strips across all disks.
(D) In RAID 2, the number of redundant disks are proportional to the log of the number of data disks. - In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.
- In a two-level memory hierarchy, the access time of the cache memory is 12 nsec and the access time of the main memory is 1.5 msec. The hit ratio is 0.98. What is the average access time of the two-level memory system?
- Match List I with List II.
List I List II A. Supervisor mode I. Entered when the processor encounters a software interrupt instruction B. Abort Mode II. Entered in response to memory fault C. Fast Interrupt Mode III. Entered whenever the processor receives an interrupt signal from a designated fast interrupt source D. Interrupt Mode IV. Entered whenever the processor receives an interrupt signal from any other source - Deallocation of stack of thread and register contexts will take place.
View More Questions
Top CUET PG Digital Logic Questions
- What is meant by factoring?
- The simultaneous equations on the Boolean variables x, y, z, and w are: x + y + z = 1, xy = 0, x + y + w = 1, xy + z = 0. The solution for x, y, z, and w, respectively, is:
- Which of the following statements are not true?
- An FPGA with an embedded logic function that cannot be programmed is said to be:
- A pulse is applied to each input of a 2-input NAND gate. One pulse goes high at t=0 and goes back low at t=1ms. The other pulse goes high at t=0 and goes back low at t=3ms. The output pulse can be described as follows:
View More Questions
Top CUET PG Questions
- Given below are two statements:
Statement I: For Plato the meaning of the word 'Justice' is basically a conception in the mind only.
Statement II: For Plato the meaning of the word 'Justice' is fixed, mind-independently
In the light of the above statements, choose the correct answer from the options given below: - What is the electron count of OS6CO182-?
- XeF4 hydrolysis gives A + B, HF, and Oxygen. Find A and B
- What is more basic in pyrol and pyridine?
- Hydrolysis of Al2C3, Be2?
View More Questions