Question

The circuit shown below is used as an instrumentation amplifier. Among the resistors used in the input stage, the value of resistance of one of the resistors (\(R^*\)) is slightly mismatched from that of the rest of the resistors (\(R\)). Assume all operational amplifiers are ideal.
Which of the following statements is/are true?

• A. The resistance mismatch introduces a gain error
• B. The resistance mismatch degrades the common mode rejection ratio (CMRR)
• C. The resistance mismatch introduces an offset error
• D. \(V_{out}\) is not sensitive to any resistance mismatch

Hint:

A perfectly balanced resistor network in the input stage is what lets an instrumentation amplifier reject common-mode signals well.

Answer 1

The Correct Option is A, B

Step 1: Identify the circuit topology.
This is a three-op-amp instrumentation amplifier.
The input stage (dashed box) has two op-amps, each in a non-inverting arrangement, and their feedback paths are tied together through a resistor network built from \(R\) and \(R^*\).
The output of this input stage feeds a standard difference amplifier built from \(R_1\) and \(R_F\), which produces \(V_{out}\).

Step 2: Recall why the input stage uses matched resistors.
In an ideal instrumentation amplifier, the resistor network between the two input-stage op-amps is built from perfectly matched resistors.
This symmetry makes both input channels amplify the common-mode part of the signal by exactly the same amount, so the difference amplifier that follows can cancel it out completely.
The same symmetric network also sets the overall differential gain of the instrumentation amplifier through a known design formula.

Step 3: Work out the effect of the resistor mismatch (\(R^*\)).
Since \(R^*\) is slightly different from \(R\), the gain network in the input stage is no longer symmetric between the two channels.
Because the differential gain of the input stage depends directly on this resistor network, the actual gain drifts away from its designed value. This is a gain error, so option (A) is true.
Because the two channels no longer amplify a common signal by the same amount, a small differential component appears at the input-stage output even when both inputs receive an identical (purely common-mode) signal. This component passes through the second-stage difference amplifier and shows up at \(V_{out}\), so the ratio of differential-mode gain to common-mode gain (the CMRR) falls. Option (B) is true.

Step 4: Rule out the remaining options.
Option (C) claims the mismatch introduces an offset error. Since all the op-amps are ideal (zero input offset voltage, infinite gain, zero bias current), a resistor mismatch alone cannot create a nonzero output when both inputs are exactly zero; it only changes how gain scales the input signal. So option (C) is false.
Option (D) claims \(V_{out}\) is insensitive to the mismatch, which directly contradicts the gain error and CMRR degradation shown in Step 3, so option (D) is false.

Final Answer:
The resistance mismatch introduces a gain error and degrades the CMRR. \[ \boxed{\text{(A), (B)}} \]