Step 1: Understand what a PLL locks onto.
A phase locked loop drives its voltage-controlled oscillator (VCO) until the two signals reaching the phase detector have the same frequency, with a fixed phase relationship between them. Once the loop is in lock, we only need to match the frequency at the two phase detector inputs.
Step 2: Identify the two signals entering the phase detector.
The input square wave first passes through a \(\div 20\) counter before it reaches the phase detector, so that input to the phase detector runs at \(f_{in}/20\).
The VCO output is fed back through a \(\div 1024\) counter before it reaches the phase detector, so that input runs at \(f_{out}/1024\).
Step 3: Write the lock condition and solve for the output frequency.
In lock, these two phase detector inputs are equal:
\[ \frac{f_{in}}{20} = \frac{f_{out}}{1024} \]
Solving for \(f_{out}\):
\[ f_{out} = f_{in} \times \frac{1024}{20} \]
With \(f_{in} = 10\) kHz:
\[ f_{out} = 10 \times \frac{1024}{20} = 10 \times 51.2 = 512 \text{ kHz} \]
Final Answer:
The steady state output frequency of the VCO is \(512\) kHz.
\[ \boxed{512 \text{ kHz}} \]