Question

Given below are two statements :
one is labelled as
Assertion (A) and the other is labelled as
Reason (R).
Assertion (A) :
In a ripple carry adder, carry propagation delay increases linearly with the number of bits.
Reason (R) :
Each bit addition must wait for the carry output from the previous stage.
In the light of the above statements, choose the most appropriate answer from the options given below :

• A. Both (A) and (R) are correct and (R) is the correct explanation of (A)
• B. Both (A) and (R) are correct but (R) is not the correct explanation of (A)
• C. (A) is correct but (R) is not correct
• D. (A) is not correct but (R) is correct

Hint:

To fix this "linear" bottleneck, modern CPUs use Carry Look-ahead Adders (CLA), which calculate carries in parallel using logic, making the delay logarithmic instead of linear.

Answer 1

The Correct Option is A

This question focuses on the timing characteristics of digital arithmetic circuits. 1. Understanding the Ripple Carry Adder (RCA): An $n$-bit RCA is constructed by cascading $n$ full adders in series. The carry output ($C_{out}$) of one full adder serves as the carry input ($C_{in}$) for the next more significant bit. 2. Evaluating Assertion (A): Because the adders are in series, the carry signal must "ripple" through every single stage before the final sum and carry are valid. If each stage has a delay of $T_{gate}$, an $n$-bit adder will have a total delay approximately equal to $n \times T_{gate}$. This is a linear relationship ($O(n)$). Thus, Assertion (A) is correct. 3. Evaluating Reason (R): The reason the delay is linear is exactly because the $i^{th}$ stage cannot determine its final carry output until it has received the carry from the $(i-1)^{th}$ stage. This sequential dependency is the root cause of the propagation delay. Thus, Reason (R) is correct and provides the direct explanation for (A).