Question

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.
Which one of the following sequences of instructions corresponds to the high-level language statement \(Z = X + Y\)?
Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.

• A.

  ADD Z, X, Y

• B.

  LOAD R0, X
  ADD Z, R0, Y

• C.

  ADD R0, X, Y
  STORE Z, R0

• D.

  LOAD R0, X
  LOAD R1, Y
  ADD R2, R0, R1
  STORE Z, R2

Hint:

In a load-store architecture only LOAD and STORE may touch memory, so X and Y must first be loaded into registers, added register-to-register, and the result stored back to Z.

Answer 1

The Correct Option is D

Step 1: Recall what a load-store architecture requires. In a load-store architecture only two kinds of instructions may touch memory, LOAD, which brings a value from memory into a register, and STORE, which writes a register's value out to memory. Every other instruction, including ADD, operates purely on registers, it cannot read or write a memory operand directly. The given instruction format, first operand is the destination, means ADD dest, src1, src2 writes its result into dest.

Step 2: Evaluate option (A), ADD Z, X, Y. Z, X, and Y are all memory operands and this single ADD is asked to read two memory operands and write a third memory operand directly. That is impossible in a load-store architecture. So (A) is invalid.

Step 3: Evaluate option (B), LOAD R0, X followed by ADD Z, R0, Y. The LOAD is fine, it brings X into R0, but the following ADD still has Z and Y as memory operands used directly inside a non-load/store instruction, again violating the rule that ADD may only use registers. So (B) is invalid.

Step 4: Evaluate option (C), ADD R0, X, Y followed by STORE Z, R0. The STORE is fine, it writes register R0 to memory location Z, but the ADD directly reads memory operands X and Y, which is not allowed since ADD must take its source operands from registers, not memory. So (C) is invalid.

Step 5: Evaluate option (D). LOAD R0, X brings X into R0 (memory to register, allowed for LOAD). LOAD R1, Y brings Y into R1 (memory to register, allowed for LOAD). ADD R2, R0, R1 computes R0 + R1 into R2 using only registers on both source and destination sides, exactly what a load-store ADD is permitted to do. STORE Z, R2 writes register R2 out to memory location Z (register to memory, allowed for STORE). Every instruction obeys the load-store rule, memory is touched only by LOAD and STORE.

Step 6: Conclusion. Only option (D) is a legal instruction sequence for a strict load-store architecture that still computes \(Z = X + Y\), so it is the correct translation.

\[ \boxed{\text{Option D}} \]