Question

Consider a pipelined processor with 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage except EX takes one cycle. The EX stage takes one cycle for ADD and two cycles for MUL. Given the instruction sequence:
\[ \text{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL} \] The speedup (rounded to 2 decimal places) is \(\underline{\hspace{2cm}}\).

Hint:

Operand forwarding significantly reduces stalls caused by data dependencies in pipelines.

Answer 1

Correct Answer: 1.87

Step 1: Execution time without operand forwarding.
Without forwarding, every data-dependent instruction must wait until the WB stage of the previous instruction completes. Due to alternating ADD and MUL instructions and dependencies, several stall cycles are introduced.
The total execution time without operand forwarding is calculated as:
\[ T_{\text{no-forward}} = 30 \text{ cycles} \]

Step 2: Execution time with operand forwarding.
With operand forwarding, data hazards are reduced. ADD results are forwarded after EX, and MUL results after their EX completion, reducing stalls significantly.
The total execution time with operand forwarding is:
\[ T_{\text{forward}} = 16 \text{ cycles} \]

Step 3: Compute speedup.
\[ \text{Speedup} = \frac{T_{\text{no-forward}}}{T_{\text{forward}}} = \frac{30}{16} = 1.875 \]

Step 4: Round to two decimal places.
\[ \text{Speedup} \approx 1.88 \] % Final Answer

Final Answer: \[ \boxed{1.88} \]