Question

Arrange 5 stage instruction pipeline operation in correct order :
A. Instruction Fetch

B. Instruction Decode Register Fetch

C. Execute ALU operation

D. Memory access

E. Write Back

Choose the correct answer from the options given below :

• A. A, C, B, E, D
• B. A, B, D, C, E
• C. B, A, C, D, E
• D. A, B, C, D, E

Hint:

Think of it like a fast-food assembly line: Fetch the order ticket, Decode what they want, Execute (cook) the food, Memory (grab a soda from the fridge), and Write Back (hand the bag to the customer).

Answer 1

The Correct Option is D

The classic RISC instruction pipeline consists of five stages that an instruction must pass through to be completed by the CPU. 1. The Five Stages in Order:
• IF - Instruction Fetch (A): The CPU reads the instruction from the memory address stored in the Program Counter.
• ID - Instruction Decode (B): The control unit decodes the instruction to determine what operation to perform and reads required values from registers.
• EX - Execute (C): The ALU performs the actual operation (addition, bitwise logic, etc.) or calculates a memory address.
• MEM - Memory Access (D): If required (like in LOAD or STORE), the CPU accesses data memory.
• WB - Write Back (E): The final result is written back into the register file. 2. Conclusion: The logical flow is Fetch $\to$ Decode $\to$ Execute $\to$ Memory $\to$ Write Back. This matches identifiers A, B, C, D, E.