Question

Arrange 5 stage instruction pipeline operation in correct order :
A. Instruction Fetch

B. Instruction Decode Register Fetch

C. Execute ALU operation

D. Memory access

E. Write Back

Choose the correct answer from the options given below :

• A. A, C, B, E, D
• B. A, B, D, C, E
• C. B, A, C, D, E
• D. A, B, C, D, E

Hint:

Think of it like a fast-food assembly line: Fetch the order ticket, Decode what they want, Execute (cook) the food, Memory (grab a soda from the fridge), and Write Back (hand the bag to the customer).

Answer 1

The Correct Option is D

Concept:
• Pipelining is a technique used in computer architecture to overlap the execution of multiple instructions.
• The classic RISC pipeline consists of five stages, where each instruction moves through these stages in a fixed sequential order.

Step 1: Identify the first stage (A)
IF (Instruction Fetch): The instruction is fetched from memory using the address in the Program Counter (PC).

Step 2: Identify the second stage (B)
ID (Instruction Decode): The instruction is decoded to identify the operation and the registers involved. Register values are also read.

Step 3: Identify the third stage (C)
EX (Execute): The Arithmetic Logic Unit (ALU) performs the actual computation (e.g., addition) or calculates an effective memory address.

Step 4: Identify the fourth stage (D)
MEM (Memory Access): If the instruction is a Load or Store, the processor accesses the data memory. Otherwise, the result bypasses this stage.

Step 5: Identify the final stage (E)
WB (Write Back): The final result (from ALU or Memory) is written back into the register file.