Question

An 8 bit successive approximation Analog to Digital Converter (ADC) has a clock frequency of 1 MHz. Assume that the start conversion and end conversion signals occupy one clock cycle each. Among the following options, what is the maximum frequency that this ADC can sample without aliasing?

• A. 0.9 kHz
• B. 9.9 kHz
• C. 49.9 kHz
• D. 99.9 kHz

Hint:

- Successive Approximation ADCs take \(N+2\) cycles (for an \(N\)-bit resolution). - Always apply Nyquist criterion: maximum input frequency \(f_{\text{max}} = f_s/2\). - Pay attention to clock overhead cycles in ADC timing.

Answer 1

The Correct Option is C

Step 1: In a successive approximation ADC, an \(N\)-bit conversion requires \(N\) clock cycles. Additionally, one clock cycle is used for the start signal and one for the end signal. Step 2: For an 8-bit ADC: \[ \text{Total cycles per conversion} = 8 + 2 = 10. \] Step 3: Clock frequency = \(1 \, \text{MHz} = 10^6 \, \text{Hz}\). Thus, conversion rate: \[ f_s = \frac{10^6}{10} = 100 \, \text{kHz}. \] Step 4: To avoid aliasing, Nyquist criterion states that the maximum input signal frequency is half the sampling frequency: \[ f_{\text{max}} = \frac{f_s}{2} = \frac{100}{2} = 50 \, \text{kHz}. \] Step 5: From the given options, the closest correct value is \(49.9 \, \text{kHz}\).