A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB
reach is defined as the total amount of physical memory that can be accessed
through the TLB entries. The paging system uses pages of size 4 KB. The virtual
address space is 64 GB and physical address space is 1 GB. If each TLB entry stores
a 4-bit process id, page number, frame number, and a 2-bit control field, then the
size of the TLB (in bytes) is ___________. (answer in integer)
Note: 1K=210, 1M=220, 1G=230
We need to find the total size of the TLB in bytes, given the TLB reach, page size, virtual address space, and physical address space.
Step 1: Find the number of entries in the TLB.
TLB reach is the total physical memory addressable through the TLB, so:
\[\text{Number of TLB entries} = \frac{\text{TLB reach}}{\text{Page size}} = \frac{1\,MB}{4\,KB} = \frac{2^{20}}{2^{12}} = 2^{8} = 256\]Step 2: Find the number of bits needed for the page number field.
Virtual address space is 64 GB and page size is 4 KB, so the number of virtual pages is:
\[\frac{64\,GB}{4\,KB} = \frac{2^{36}}{2^{12}} = 2^{24}\]So the page number field requires 24 bits.
Step 3: Find the number of bits needed for the frame number field.
Physical address space is 1 GB and frame size is 4 KB, so the number of physical frames is:
\[\frac{1\,GB}{4\,KB} = \frac{2^{30}}{2^{12}} = 2^{18}\]So the frame number field requires 18 bits.
Step 4: Compute the size of one TLB entry.
Each TLB entry contains a 4-bit process id, the page number field, the frame number field, and a 2-bit control field:
\[4 + 24 + 18 + 2 = 48 \text{ bits} = \frac{48}{8} = 6 \text{ bytes}\]Step 5: Compute the total size of the TLB.
\[\text{Total TLB size} = \text{Number of entries} \times \text{Size per entry} = 256 \times 6 = 1536 \text{ bytes}\]\[\boxed{1536 \text{ bytes}}\]
A schedule of three database transactions \(T_1\), \(T_2\), and \(T_3\) is shown. \(R_i(A)\) and \(W_i(A)\) denote read and write of data item A by transaction \(T_i\), \(i = 1, 2, 3\). The transaction \(T_1\) aborts at the end. Which other transaction(s) will be required to be rolled back?

Consider a system that has a cache memory unit and a memory management unit
(MMU). The address input to the cache memory is a physical address. The MMU
has a translation lookaside buffer (TLB). Assume that when a page is evicted from
the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can
NEVER happen?
Consider contiguous allocation of physical memory to processes using variable
partitioning scheme. Suppose there are 8 holes in the memory of sizes 20 KB, 4 KB,
25 KB, 18 KB, 7 KB, 9 KB, 15 KB, and 12 KB. Assume that no two holes are
adjacent. Two processes P1 of size 16 KB and P2 of size 9 KB arrive in that order,
and they are allocated memory using the best-fit technique. After allocating space
to P1 and P2, the number of holes of size less than 8 KB is ____________. (answer
in integer)
Note: 1K=210