Question

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is \(\underline{\hspace{1cm}}\).

Hint:

The speedup in a processor with a branch predictor can be calculated using the accuracy of the predictor and the penalty for mispredictions, which in turn affects the overall CPI.

Answer 1

Correct Answer: 1.42 - 1.45

The base CPI for X1 is 1. The number of cycles required for X1 depends on the number of branch instructions. Since 30% of the instructions are branch instructions, and there are 2 cycles of stalls for every branch: \[ \text{CPI}_{\text{X1}} = 1 + 0.3 \times 2 = 1 + 0.6 = 1.6. \] The clock frequency for both processors is 2 GHz, so the clock cycle time is: \[ \text{Clock cycle time} = \frac{1}{\text{Clock frequency}} = \frac{1}{2 \times 10^9} = 0.5 \, \text{ns}. \] Now, consider processor X2. The base CPI remains 1, but the branch predictor eliminates stalls for correctly predicted branches. Since the predictor has 80% accuracy, the number of cycles saved for correctly predicted branches is: \[ \text{CPI}_{\text{X2}} = 1 + 0.3 \times 0.2 \times 2 = 1 + 0.12 = 1.12. \] The speedup is the ratio of the CPI for X1 to the CPI for X2: \[ \text{Speedup} = \frac{\text{CPI}_{\text{X1}}}{\text{CPI}_{\text{X2}}} = \frac{1.6}{1.12} \approx 1.43. \] Thus, the speedup obtained by X2 over X1 is: \[ \boxed{1.43}. \]