Question

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds.
The register delay between stages is 5 nanoseconds. The total time to execute 100 independent instructions is \(\underline{\hspace{2cm}}\) nanoseconds.

Hint:

Pipeline execution time depends on the slowest stage, not the sum of all stage delays.

Answer 1

Correct Answer: 17160

The clock cycle time of a pipeline is determined by the slowest stage plus register delay.
\[ \text{Maximum stage delay} = 160 \text{ ns} \] \[ \text{Clock cycle time} = 160 + 5 = 165 \text{ ns} \] For a pipeline with 5 stages, total cycles required for 100 instructions: \[ = (100 + 5 - 1) = 104 \text{ cycles} \] \[ \text{Total execution time} = 104 \times 165 = 17160 \text{ ns} \] Final Answer: \[ \boxed{17160} \]