- Option (A): The TLB (Translation Lookaside Buffer) performs an associative search on its valid entries to speed up the translation of virtual addresses to physical addresses. This is a true statement, as the TLB indeed operates by searching all its entries in parallel.
- Option (B): If there is a TLB hit for a given address but later a cache miss occurs, this implies the cache was not able to find the corresponding data. However, the word will still be present in main memory, as the memory management unit ensures that data is eventually fetched from there. This is a true statement.
- Option (C): Inverted page tables work by using a hash function or an indexed lookup to convert virtual addresses. The time taken to perform lookups might differ depending on the actual address and lookup structure. Hence, the statement that the access time is always the same for all incoming virtual addresses is false.
- Option (D): In systems using hashed page tables, when two different virtual addresses map to the same hash value (a collision), the memory access time for those addresses can differ because collision resolution mechanisms like chaining or open addressing are used, resulting in additional time for lookup. This is a true statement.
Final Answer: (C)