Question

Which of the following functions represent(s) the output of the CMOS logic-gate shown in the circuit below?

• A. \(f= \overline{A} + \overline{B}\cdot\overline{C}\)
• B. \(f= \overline{A+BC}\)
• C. \(f= \overline{A}\cdot(\overline{B} + \overline{C})\)
• D. \(f= \overline{A\cdot(B + C)}\)

Hint:

Trace the NMOS pull-down network: A alone in parallel with (B in series with C), so \(f=\overline{A+BC}\); check the PMOS side too, since the two halves of this circuit do not form a valid complementary pair.

Answer 1

The Correct Option is B, C

Step 1: Trace the pull-up (PMOS) network from VDD to the output f.
Reading the circuit from top to bottom: a single PMOS transistor with gate \(C\) sits directly under \(V_{DD}\); its drain lands on an internal node, call it \(N1\). From \(N1\), two PMOS transistors run down to the output node \(f\) side by side, one gated by \(A\) and one gated by \(B\), so these two are in parallel with each other.
This gives a pull-up path: the \(C\)-gated PMOS in series with the parallel pair of \(A\)-gated and \(B\)-gated PMOS. A series PMOS conducts when its gate input is \(0\), and a parallel branch conducts when either PMOS in it is \(0\), so this network pulls \(f\) to \(V_{DD}\) (logic \(1\)) when
\[ C=0 \ \text{AND}\ (A=0\ \text{OR}\ B=0) \]
Step 2: Trace the pull-down (NMOS) network from f to ground.
Below \(f\), the \(A\)-gated NMOS runs straight down to ground on its own. On the other side, the \(B\)-gated NMOS is stacked in series with the \(C\)-gated NMOS, and that series pair also runs from \(f\) down to ground, in parallel with the lone \(A\)-gated NMOS. An NMOS conducts when its gate is \(1\), and a series stack conducts only when both transistors in it are \(1\), so this network pulls \(f\) to ground (logic \(0\)) when
\[ A=1 \ \text{OR}\ (B=1\ \text{AND}\ C=1) \]
Step 3: Turn the pull-down condition into a Boolean expression for f.
The pull-down network conducting is exactly the condition for \(f=0\), so \(f=0\) when \(A+BC=1\), which means \(f\) is the complement of that expression:
\[ f = \overline{A+BC} \]
Applying De Morgan's theorem to expand this,
\[ f = \overline{A}\cdot\overline{BC} = \overline{A}\cdot(\overline{B}+\overline{C}) \]
This is exactly option (B) in its unexpanded form, \(f=\overline{A+BC}\), and exactly option (C) in its expanded form, \(f=\overline{A}\cdot(\overline{B}+\overline{C})\). They are algebraically the SAME function, just written two different ways, so both (B) and (C) are correct descriptions of what the pull-down network computes.
Step 4: Check this against the pull-up network, and notice a genuine mismatch.
For a standard, valid static CMOS gate, the PMOS pull-up network must be the exact dual of the NMOS pull-down network (series legs on one side become parallel legs on the other, using the same transistor gate labels), so that pull-up and pull-down are never both on or both off for the same input. The dual of "\(A\) alone, in parallel with \(B\) in series with \(C\)" should be "\(A\) in series with (\(B\) in parallel with \(C\))".
But the pull-up network actually drawn here has \(C\) as the lone series transistor, with \(A\) and \(B\) forming the parallel pair, which is NOT the dual of the pull-down network (the dual should have used \(A\) as the lone series transistor, matching \(A\) being the lone parallel branch on the pull-down side). Working out the pull-up condition directly gives \(f=\overline{C}\cdot(\overline{A}+\overline{B})\), which is a different Boolean function altogether and does not match any of the four printed options.
Step 5: See what this mismatch does to the actual circuit behaviour.
Checking all \(8\) input combinations of \(A,B,C\) against both networks as literally drawn shows two problem cases. At \(A{=}0,B{=}0,C{=}1\): the pull-up network is off (since \(C=1\) blocks the top PMOS) and the pull-down network is also off (since \(A=0\) and \(BC=0\)), so the output \(f\) is left floating, driven by neither rail. At \(A{=}1,B{=}0,C{=}0\): the pull-up network is on (\(C=0\) turns on the top PMOS, and \(A=0\)... more precisely \(A'+B'=1\) since \(B=0\) gives \(B'=1\)) at the same time as the pull-down network is on (since \(A=1\)), so \(V_{DD}\) and ground are shorted together through the gate. Neither of these is possible in a correctly designed static CMOS gate, which confirms the circuit as drawn is not internally consistent. This is exactly why GATE withdrew this question and credited every candidate with marks, rather than expecting a single unambiguous option to be picked.
Step 6: State the best-supported answer.
Reading the pull-down network, which is unambiguous and gives a clean, standard AND-OR structure, \(f\) works out to \(\overline{A+BC}=\overline{A}\cdot(\overline{B}+\overline{C})\), matching options (B) and (C). Options (A) and (D) are also equal to each other (\(\overline{A}+\overline{B}\cdot\overline{C}=\overline{A\cdot(B+C)}\) by direct expansion), but they belong to a different Boolean function that does not match the pull-down network reading, so they are not supported.
Final Answer:
\[ \boxed{f = \overline{A+BC} = \overline{A}\cdot(\overline{B}+\overline{C})\ \text{(options B and C)}} \]
Note: GATE officially declared this question ambiguous or flawed and awarded marks to all candidates (MTA).