In the circuit shown, the initial binary content of shift register A is $1101$ and that of shift register B is $1010$. The shift registers are positive–edge triggered, and the gates have no delay. When the shift control is high, what will be the binary content of the shift registers A and B after four clock pulses?
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In cascaded shift registers, the downstream register copies the upstream register’s word after as many clocks as the word length; the exact logic forming the serial input sets the new pattern of the upstream register.
When the shift control is high, both registers shift right at each positive clock edge. Register B’s serial input is taken from the serial output of register A, so over four clocks B copies the $4$-bit word from A and ends up with 1101.
Register A’s serial input is formed by the OR of a complemented tap from A and the serial output feeding from the other register; iterating the shift for four pulses yields the pattern 0101 in A. Hence after four pulses, \fbox{A = 0101, B = 1101}.
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