In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of the following logic operations is realized by the circuit?
Show Hint
Series PMOS in the pull-up network together with parallel NMOS in the pull-down network is the standard CMOS structure for a NOR gate.
Step 1: Identify the pull-up network. Two PMOS transistors are stacked in series between \(+V_{DD}\) and the output node Y, one gated by A and one gated by B. A PMOS transistor conducts when its gate is at logic \(0\). Since the two PMOS devices are in series, current can reach Y from \(V_{DD}\) only when both PMOS transistors conduct together, which needs both A and B at logic \(0\).
Step 2: Identify the pull-down network. Two NMOS transistors sit in parallel between Y and ground, one gated by A and one gated by B. An NMOS transistor conducts when its gate is at logic \(1\). Because the two NMOS devices are in parallel, Y gets pulled to ground if either A or B, or both, is at logic \(1\).
Step 3: Build the truth table. When \(A=0,B=0\): both PMOS conduct, giving \(Y=1\); both NMOS are off, so there is no conflicting path to ground. When \(A=0,B=1\): the PMOS gated by B turns off, breaking the series pull-up path, while the NMOS gated by B turns on, pulling \(Y=0\). When \(A=1,B=0\): by the same reasoning with the roles swapped, \(Y=0\). When \(A=1,B=1\): both PMOS are off and both NMOS conduct, so \(Y=0\).
Step 4: Match the truth table to a logic function. \(Y\) is \(1\) only when both A and B are \(0\), and \(Y\) is \(0\) for every other input combination. This is exactly the truth table of the NOR function, \(Y=\overline{A+B}\).
Step 5: Rule out the other options. OR would give \(Y=1\) whenever A or B is \(1\), the opposite of what this circuit produces. XOR would give \(Y=1\) only when A and B differ, which does not match the row \(A=0,B=0\) giving \(Y=1\) here. AND would need a series NMOS pull-down and a parallel PMOS pull-up, which is the reverse of this circuit's structure.
Final Answer: The circuit realizes the NOR function. This is the standard static CMOS structure: series PMOS in the pull-up network paired with parallel NMOS in the pull-down network always gives a NOR gate. \[ \boxed{\text{NOR}} \]
