For a MOS capacitor, $V_{fb}$ and $V_t$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ($W_{\text{dep}}$) for varying gate voltage ($V_g$) is best represented by
A
B
C
D
Step 1: Accumulation ($V_g \ll V_{fb}$).
Majority carriers accumulate at the surface $\Rightarrow W_{\text{dep}}\approx 0$.
Step 2: Depletion ($V_{fb}<V_g<V_t$).
A depletion region forms and widens with $V_g$. For a p–type substrate (nMOS case), \[ W_{\text{dep}}=\sqrt{\frac{2\varepsilon_s\,\psi_s}{qN_A}}\Rightarrow W_{\text{dep}}\ \text{increases roughly as}\ \sqrt{\psi_s}\ \text{with}\ V_g . \]
Step 3: Strong inversion ($V_g \ge V_t$).
Further increase in $V_g$ is primarily taken up by inversion charge, not by widening depletion. Hence $W_{\text{dep}}$ saturates at \[ W_{\max}=\sqrt{\frac{2\varepsilon_s(2\Phi_F)}{qN_A}}\ \ \text{(constant)}. \]
Step 4: Match with the plots.
The correct curve starts near zero in accumulation, rises in depletion (from $V_{fb}$), and then flattens to a constant beyond $V_t$ $\Rightarrow$ Option (B). \[ \boxed{\text{The depletion width increases from }V_{fb}\text{ and saturates beyond }V_t\ \Rightarrow\ \text{(B)}} \]

A JK flip-flop has inputs $J = 1$ and $K = 1$.
The clock input is applied as shown. Find the output clock cycles per second (output frequency).

f(w, x, y, z) =\( \Sigma\) (0, 2, 5, 7, 8, 10, 13, 14, 15)
Find the correct simplified expression.
For the non-inverting amplifier shown in the figure, the input voltage is 1 V. The feedback network consists of 2 k$\Omega$ and 1 k$\Omega$ resistors as shown.
If the switch is open, $V_o = x$.
If the switch is closed, $V_o = ____ x$.

Consider the system described by the difference equation
\[ y(n) = \frac{5}{6}y(n-1) - \frac{1}{6}(4-n) + x(n). \] Determine whether the system is linear and time-invariant (LTI).