Question

Consider a processor that generates 32-bit virtual addresses. It uses a direct mapped cache whose size is 32 KByte and has 32 Byte blocks. What is the number of bits needed for cache addressing?

• A. 5
• B. 10
• C. 15
• D. 20

Hint:

Cache addressing bits are calculated as: Index bits + Block offset bits.

Answer 1

The Correct Option is C

Step 1: Understanding cache parameters.
Cache size = 32 KB = $2^{15}$ bytes
Block size = 32 bytes = $2^5$ bytes
Step 2: Calculating number of cache blocks.
\[ \text{Number of blocks} = \frac{2^{15}}{2^5} = 2^{10} \]
Step 3: Calculating block offset bits.
Block size is $2^5$ bytes, so block offset requires $5$ bits.
Step 4: Calculating index bits.
Number of cache blocks is $2^{10}$, so index bits required are $10$.
Step 5: Total cache addressing bits.
Cache addressing bits = Index bits + Block offset bits
\[ 10 + 5 = 15 \]
Step 6: Final conclusion.
Thus, the number of bits needed for cache addressing is 15.

Answer 2

We need the total number of bits required to address a location within the 32 KB direct-mapped cache, given 32-byte blocks. A direct-mapped cache address splits into a block offset (locating a byte within a block) and a block index (locating which cache line/block), so let's check each candidate against that structure:

1. 5 bits: This matches only the block offset ( \( \log_2 32 = 5 \) ), i.e. the bits needed to pick a byte inside one 32-byte block. It ignores the need to pick which of the many blocks the byte belongs to, so 5 bits alone can't address the whole cache.
2. 10 bits: This matches only the block index. The cache holds \( \frac{32\text{KB}}{32\text{B}} = 2^{10} \) blocks, so 10 bits identify one block, but not the byte position inside it.
3. 15 bits: This is the block index (10 bits) plus the block offset (5 bits) combined, \(10+5=15\). Together, these two fields let you address any individual byte anywhere in the 32 KB cache, which is what "cache addressing" requires.
4. 20 bits: This does not correspond to any natural field of this cache. It doesn't match the offset, the index, or their sum, so it isn't consistent with the cache's actual dimensions.

Only combining the index and offset fields gives a complete address into the cache, and that total is 15 bits.

Therefore, the correct answer is 15.