Question

An SAR type ADC and a Flash type ADC have identical resolution and reference voltage. If both of them have same input signal bandwidth and sampling rate, then which of the following statements is true?

• A. Flash ADC consumes comparators exponentially
• B. SAR ADC has better DNL performance inherently
• C. SAR ADC has lower conversion latency always
• D. Flash ADC has a simpler analog layout architecture

Hint:

An \(n\)-bit Flash ADC requires \(2^n - 1\) comparators, making it ultra-fast but hardware-heavy. An \(n\)-bit SAR ADC requires only 1 comparator but takes \(n\) clock cycles to complete its conversion.

Answer 1

The Correct Option is A

Concept: Analog-to-Digital Converters (ADCs) employ different architectural methods to convert analog signals into digital words.
• Flash ADC Architecture: Uses a continuous string of resistors to divide a reference voltage into equal increments, with each node connected to a dedicated analog comparator. This allows the system to compare the input signal against all reference steps simultaneously, completing the conversion in a single clock cycle. However, an \(n\)-bit Flash ADC requires exactly \(2^n - 1\) individual comparators. This means the component count scales exponentially (\(\mathcal{O}(2^n)\)) with resolution.
• Successive Approximation Register (SAR) ADC Architecture: Uses a single analog comparator alongside a digital-to-analog converter feedback loop. It runs a binary search algorithm, checking one bit at a time from the most significant bit to the least significant bit. This process requires \(n\) clock cycles to complete an \(n\)-bit conversion.

Step 1: Comparing component scaling properties.
Let us look at how the number of required internal comparators changes as the resolution increases for both types of ADCs: [h!] {|c|c|c|} Resolution (\(n\) bits) & SAR ADC Comparator Count & Flash ADC Comparator Count (\(2^n - 1\))
4 bits & 1 & \(2^4 - 1 = 15\)
6 bits & 1 & \(2^6 - 1 = 63\)
8 bits & 1 & \(2^8 - 1 = 255\)
10 bits & 1 & \(2^{10} - 1 = 1023\)
This table clearly demonstrates that the hardware complexity and comparator consumption of the Flash ADC grow exponentially as the bit resolution increases.

Step 2: Evaluating the alternate choices.

• Choice (B) is incorrect: Flash ADCs generally provide comparable or better Differential Nonlinearity (DNL) at low resolutions because their resistor ladders can be matched precisely, whereas SAR DNL depends heavily on the internal DAC array matching accuracy.
• Choice (C) is incorrect: A Flash ADC completes its conversion in a single clock cycle, whereas an SAR ADC requires at least \(n\) clock cycles. Therefore, Flash ADCs always provide much lower conversion latency.
• Choice (D) is incorrect: Because a Flash ADC requires hundreds or thousands of individual comparators and a complex priority encoder layout, its analog circuit layout is far more complex than the small hardware footprint of an SAR ADC. Consequently, statement (A) is the only true option.