A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation \(b_7b_6b_5b_4b_3b_2b_1b_0\) of the content of the shift register immediately after the \(5^{th}\) clock transition (positive edge)?
Show Hint
Trace the D flip-flop and XOR feedback state after each clock edge, five times.
Step 1: Read the feedback path of the circuit.
The 8-bit register shifts left on every clock edge, so on each edge every bit moves one place towards \(b_7\) and \(b_7\) itself is pushed out of the register. That bit which leaves \(b_7\) is wired to the \(D\) input of the flip-flop. The flip-flop's \(Q\) output goes to one input of the XOR gate, and the other XOR input is tied permanently to logic \(1\). The XOR output feeds the serial input at \(b_0\). Since the XOR gate has no propagation delay, this output is ready in time for the very same clock edge that also updates the flip-flop and the register.
Step 2: Write the update rule for each block.
Let the register content after the \(n^{th}\) clock edge be \(b_7^{(n)}b_6^{(n)}\cdots b_0^{(n)}\), and let \(Q^{(n)}\) be the flip-flop output after the \(n^{th}\) edge. An XOR gate with one input tied to \(1\) is simply an inverter on its other input, so the serial bit entering \(b_0\) is the complement of the flip-flop's present output. This gives
\[
Q^{(n+1)}=b_7^{(n)}
\]
\[
b_7^{(n+1)}=b_6^{(n)},\ b_6^{(n+1)}=b_5^{(n)},\ \ldots,\ b_1^{(n+1)}=b_0^{(n)}
\]
\[
b_0^{(n+1)}=\overline{Q^{(n)}}
\]
Step 3: Set the initial condition.
Both the register and the flip-flop start cleared, so
\[
b_7^{(0)}b_6^{(0)}b_5^{(0)}b_4^{(0)}b_3^{(0)}b_2^{(0)}b_1^{(0)}b_0^{(0)}=00000000,\qquad Q^{(0)}=0
\]
Step 4: Trace edges 1 through 5.
Edge 1: \(Q^{(1)}=b_7^{(0)}=0\); the register shifts left and \(b_0^{(1)}=\overline{Q^{(0)}}=\overline{0}=1\). New state: \(00000001\).
Edge 2: \(Q^{(2)}=b_7^{(1)}=0\); shift left, \(b_0^{(2)}=\overline{Q^{(1)}}=\overline{0}=1\). New state: \(00000011\).
Edge 3: \(Q^{(3)}=b_7^{(2)}=0\); shift left, \(b_0^{(3)}=\overline{Q^{(2)}}=\overline{0}=1\). New state: \(00000111\).
Edge 4: \(Q^{(4)}=b_7^{(3)}=0\); shift left, \(b_0^{(4)}=\overline{Q^{(3)}}=\overline{0}=1\). New state: \(00001111\).
Edge 5: \(Q^{(5)}=b_7^{(4)}=0\); shift left, \(b_0^{(5)}=\overline{Q^{(4)}}=\overline{0}=1\). New state: \(00011111\).
Step 5: Analyze the options.
(A) 00011111: Matches the state obtained after the 5th clock edge. Correct.
(B) 10111111: Would need the MSB to turn 1 while six low bits also turn 1, which does not match a slow left shift of single 1s entering at \(b_0\). Incorrect.
(C) 00111111: This is the state reached after 6 clock edges, one edge too many. Incorrect.
(D) 11000011: Does not match any reachable state of this feedback chain within the first five edges. Incorrect.
Step 6: Final conclusion.
After the 5th clock transition the register holds
\[
\boxed{00011111}
\]
